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This test models the phenomenon in which semiconductors and electronic parts become charged due to friction and contact, and rapid discharge occurs when the charged parts contact a conductor. ESD does not incur any defects if it can be implemented in a only No Charge or only No Discharge environment. However, since it is impossible to remove the source of static electricity, the level of tolerance of ICs and electronic components must be assessed.

Semiconductor(Memory, System IC), DIscrete IC, Passive Component Level ESD(CDM) Test, Board-level CBM (Charged Board Model) Test