Test Analysis & Equipment Utilization

Electrostatic Discharge

ESD, one of the major causes of device failures in the semiconductor industry, is a rapid transfer of electrostatic charge between two objects when two objects at different potentials come into direct contact with each other. A human body loses or gain charges by several modes, which is charged to positive or negative potential. Several models where ESD events occur were developed and ESD sensitivity was classified into grades according to testing levels. (Classification)
ESD Test Models - 1. Human Body Model, 2. Machine Model, 3. Charged Device Model

Summary of ESD

Human Body Model (HBM)

As described above, the HBM simulates the ESD event when a person charged either to a positive or negative potential touches an IC that is at another potential. After organizing a circuit simulating the characteristics of a human body, apply ESD pulse to it. HBM classification level ranges 250 V ~ 8000 V.

Machine Model (MM)

The MM simulates the ESD event that occurs when a part of an equipment or tool comes into contact with a device at a different potential during the semiconductor manufacturing process. MM classification level ranges 50 V ~ 400 V.

Charged Device Model(CDM)

Considered to be the most close to field failures, the CDM simulates the ESD event wherein a device charges to a certain potential, and then gets into contact with a conductive surface at a different potential. CMD classification level ranges 200 V ~ 1000 V.

Human Body Model (HBM)
Human Body Model (HBM)
Machine Model (MM)
Machine Model (MM)
Charged Device Model(CDM)
Charged Device Model(CDM)

Reference Documents

  • JESD22 B110 “For Electrostatic Discharge Sensitivity Testing (HBM)”
  • AEC-Q100-002 “Human Body Model Electrostatic Discharge Test”
  • AEC Q101-001 “Human Body Model Electrostatic Discharge Test”
  • JESD22-A115 “Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)”
  • AEC-Q100-003 “Machine Model Electrostatic Discharge Test”
  • AEC-Q101-002 “Machine Model (MM) Electrostatic Discharge (ESD)Test”
  • JESD22-C101 “ Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand Thresholds of Microelectronic Components”
  • AEC-Q100-011 “Charged-Device Model (CDM) ) Electrostatic Discharge Test”
  • AEC-Q101-005 “Capacitive Discharge Model (CDM) Electrostatic Discharge Test”
ESD Tester–MK2
ESD Tester–MK2

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (Ex: a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS).

An SCR is a 3-terminal 4-layered p-n-p-n device that basically consists of a PNP transistor and an NPN transistor as shown in Figure. An SCR is 'off' during its normal state but will conduct current in one direction (from anode to cathode) once triggered at its gate, and will do so continuously as long as the current through it stays above a 'holding' level.

This is easily seen in Figure, which shows that 'triggering' the emitter of T1 into conduction would inject current into the base of T2. This would drive T2 into conduction, which would forward bias the emitter-base junction of T1 further, causing T1 to feed more current into the base of T2. Thus, T1 and T2 would feed each other with currents that would keep both of them saturated.

The best defense against latch-up is good product design. There are now many design-for-reliability guidelines for reducing the risk of latch-up, many of which can be as simple as putting diodes in the right places to prevent parasitic devices from turning on. Of course, preventing a device from being subjected to voltages that exceed the absolute maximum ratings is also to be observed at all times.

Parasitic thyristor causes Latch Up
Parasitic thyristor causes Latch Up

Reference Documents

  • JJESD22-78 “Latch-up”
Latch Up Tester and Test socket board
Latch Up Tester and Test socket board
EOS ,Electrical Overstress, is a major cause of failure in the semiconductor products, and it causes destructive phenomenon by exceeded electro-magnetic signals and overvoltage in semiconductor devices and system circuits. Because EOS(1us~) longer lasts than ESD(a few ns), it can cause a wide damage to semiconductor devices.

Case study of failure analysis by EOS

Case study of failure analysis by EOS

EOS Qualification Test

When IC or electronic components impact on surge, general criteria of its tolerance can be established. With this test, tolerance level of IC by EOS surge can be determined by minimum guarantee level for each test pin combination and polarity through final testing result.

Combination waveform TEST TIME
OCV(Open Circuit Voltage) SCC(Short Circuit Current)

Rising : 1.2㎲ ± 20%
Duration : 50㎲ ± 30%

Rising : 8㎲ ± 20%
Duration : 20㎲ ± 30%
3 times

EOS Pulse Specification (IEC 61000-4-5)

EOS Reproduction Test

For reproduction of field failure by EOS, intentional failure is caused in a good sample by EOS. And then, weakness of products by EOS can be improved through failure mechanism analysis in comparison with field failure device.